CAES develops 16-core RISC-V microprocessor for space

CAES (Cobham Advanced Electronic Solutions) said it was awarded a contract from the European Space Agency (ESA) to develop a 16-core, space-hardened microprocessor based on the open architecture of the RISC-V instruction set (ISA). Funded by the Swedish National Space Agency, the project will involve the design of a fault and radiation tolerant system on a chip that will improve performance and energy efficiency in satellite and spacecraft applications.

The GR7xV processor will be designed into space controls and payload data management and processing systems to enable new types of observation, communication, navigation and scientific missions and services. These include advanced and flexible telecommunications satellite payloads, science and Earth observation payloads, and robotic systems such as planetary exploration rovers.

The new fault and radiation tolerant processor will extend CAES Gaisler’s LEON processor product family, which have been used in space applications for decades and are based on the older 32-bit SPARC V8 ISA. Several versions of the LEON processor include the LEON5 which primarily targets high-end FPGAs and deep submicron ASIC technologies, and the LEON3 for legacy and lower performance technologies. The LEON3 kernel is a reimplementation of the SPARC V8 architecture, with a deeper 7-stage pipeline and multiprocessor support, and it is distributed as part of the GRLIB IP library, and suitable for implementation on ASIC and radiation technologies. Tolerant FPGAs from Actel and Xilinx. The LEON5 kernel further improves performance over previous generations thanks to a dual problem pipeline, improved branch prediction and late ALU.

The first synthesizable VHDL model released by CAES of a processor that implements the RISC-V architecture is the NOEL-V, which can be implemented as a dual-emission processor, allowing up to two instructions per cycle to be executed. in parallel. This image shows an example implementation on the Arty A7 development board: Artix-7 FPGA. (SOURCE: CAES)

Meanwhile, CAES’s first synthesizable VHDL model of a processor that implements the RISC-V architecture is the NOEL-V, which can be implemented as a dual-emission processor, allowing up to two instructions per cycle. ‘be executed in parallel. To support the pipeline instruction emission rate, NOEL-V has advanced branch prediction capabilities. The NOEL-V cache controller supports a FIFO buffer with a sustained throughput of one cycle per memory and broad support for AHB slaves to enable fast memories and rapid cache filling.

It is interfaced using the AMBA 2.0 AHB bus and supports the plug & play method of the IP kernel provided in the CAES IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and the register file. NOEL-V can be synthesized with popular synthesis tools such as Xilinx Vivado, Synplify, and Synopsys DC, and the processor model is highly portable between different implementation technologies.

Sandi Habinc, General Manager of CAES Gaisler Products, said: “The contract with ESA further advances our development of a space-grade fault-tolerant and radiation-tolerant microprocessor with unparalleled performance for its class. The RISC-V open ISA has been widely adopted in other markets, and this project is the first to develop a RISC-V-based ASIC for space applications.

Elodie Viau, Director of Telecommunications and Integrated Applications at ESA, commented: “ESA is proud to work with CAES on this new technological development as it will enable future missions and advance the technological standard for space processors.

ESA’s contract follows a contract awarded earlier this year by Vinnova, the Swedish innovation agency, to extend the RISC-V processor platform to space-hardened applications for temporal isolation and cybersecurity. The results of this study will be used to advance the development of the space-hardened GR7xV microprocessor and will be shared with the industry as a whole. Once completed, a multi-core NOEL-V processor development platform will be tested in a partnership with Chalmers University of Technology and atsec, an independent information security-focused lab, to ” ensure maximum security towards the upper software layers.

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