RISC-V microprocessor-based framework supporting LiM operations

A new technical paper entitled “RISC-Vlim, a RISC-V framework for in-memory logic architectures” has been published by researchers from Politecnico di Torino (Italy), University of Tor Vergata (Italy) and the University of Twente (Netherlands). ).

“Most modern CPU architectures are based on the von Neumann principle, where memory and processing units are separate entities. Although the performance of processing units has improved over the years, memory capacity has not followed the same trend, creating a performance gap between them. This problem is known as a “memory wall” and severely limits the performance of a microprocessor. One of the most promising solutions is the “in-memory logic” approach. It consists of merging memory and logic units, allowing data to be processed directly inside the memory itself. Here we propose a RISC-V framework that supports in-memory logical operations. We replace data memory with a circuit that can store data and perform calculations in memory. The framework is based on a standard memory interface, so different in-memory logic architectures can be inserted inside the microprocessor, based on both CMOS and emerging technologies. The main advantage of this framework is the ability to compare the performance of different in-memory logic solutions on code execution. We demonstrate the effectiveness of the framework using CMOS volatile memory and memory based on a new emerging technology, racetrack logic. The results demonstrate an improvement in the execution speed of the algorithms and a reduction in energy consumption.

Find it spec sheet here. Published in September 2022.

Coluccio, A.; Ieva, A.; Riente, F.; Roche, M.; Ottavi, M.; Vacca, M. RISC-Vlim, a RISC-V framework for in-memory logic architectures. Electronics 2022, 11, 2990. https://doi.org/10.3390/electronics11192990.

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